1. Field of the Invention
The present invention relates to a data writing and reading apparatus, and more particularly to a data writing and reading apparatus for splitting N-bit data into M-bit data (where M is equal to or lesser than N), converting the split M-bit data into an analog signal and storing the analog signal in a nonvolatile analog memory.
2. Description of the Related Art
EEPROMs (Electrically Erasable Programmable Read Only Memory) are widely used nonvolatile memory devices. An example of a conventional EEPROM device includes a modified MOS transistor having a floating gate 1 which is electrically insulated from a peripheral element and used as a charge storage gate, as shown in FIG. 1. The EEPROM maintains the state of stored data in the absence of a power source through ion implantation into or ion emission from the floating gate 1. However, since conventional EEPROM devices store data in a digital format, eight EEPROM cells are needed in order to store the eight bits of data that constitute a byte.
An EEPROM cell consists of two transistors, as shown in FIG. 1. One transistor is a memory transistor MEM TR for storing a digital data bit at a logical "1" or "0" state. The other transistor is a select transistor SEL TR for selecting a memory bit. The memory transistor MEM TR has a double layer gate structure consisting of a control gate 2 in an upper gate layer and a floating gate 1 in a lower gate layer, wherein the floating gate 1 is electrically isolated for storing an electron or electrons. The floating gate 1 includes a very thin silicon oxide layer region 3. To implant or emit an electron from the floating gate 1, a high voltage is applied to the silicon oxide layer region 3 in order to induce an F-N current of electrons tunneling through the oxide layer.
In the electron implanting operation involving floating gate 1, which is performed to erase the logical state of the EEPROM cell, a high voltage level, typically 20 volts (V), is applied to the control gate 2 and a select gate 4. A voltage level of 0V is applied to a source electrode 5 and a drain electrode 6. This activates select transistor SEL TR and the voltage level of 0V at the drain electrode 6 is supplied to a source electrode 7, which is an N+ diffusion region positioned underneath thin silicon oxide layer region 3, of the select transistor MEM TR. Since the control gate 2 is at 20V, the F-N current flows to the source electrode 7 from the floating gate 1 and electrons are implanted on floating gate 1. In this manner, electron implantation erases the state of the logic state of the memory cell.
In an electron emitting operation, by which the logic state of the memory cell is programmed, a voltage of 0V is applied to the control gate 2 and a voltage of 20V is applied to the select gate 4 and drain electrode 6. This activates select transistor SEL TR and the voltage level of 20V applied to the drain electrode 6 also appears at the source electrode 7 of the select transistor SEL TR. Since the control gate 2 is at 0V, a high electric field is generated on the floating gate 1 from source electrode 7 which causes electrons to emit from floating gate 1 and tunnel through the thin oxide layer region 3 onto source electrode 7. In this manner, the electrons of floating gate 1 are emitted and the logic state of the memory cell is programmed.
During the write operation, a voltage level of about 5V is applied to the source electrode 5. The reason for this is that if the voltage of the source electrode 5 is 0V, then a potential drop occurs between the source electrode 7 and the drain electrode 6 of 20V and the electric field between control gate 2 and source electrode 7 will be insufficient to obtain the F-N current needed to obtain electron tunneling from floating gate 1. Therefore, a 5V potential is applied to the source electrode 5.
When an electron is implanted on floating gate 1, a threshold voltage of the memory transistor MEM TR is increased. If an electron is emitted from floating gate 1, the threshold voltage of the memory transistor MEM TR is decreased. The difference in the threshold voltage between the implanted (erased) state and the emitted (programmed) state corresponds to a logical "1" or "0" level of the data bit of the memory cell. However, since a conventional EEPROM stores only a logical "1" or "0" level by using a fixed drain voltage, an integrated state of the EEPROM device cannot be stored.
To improve such an integration problem of the memory device, U.S. Pat. No. 4,890,259 entitled "HIGH DENSITY IC ANALOG SIGNAL WRITING AND READING SYSTEM" describes a technique for directly storing an audio signal by using not only logical "1" and "0" levels but also a median level of the drain voltage mapped to an analog data signal instead of applying the fixed drain voltage during the write operation of the memory device, as shown in FIG. 2.
To describe this technique in more detail, an analog audio signal applied to microphone 29 is filtered through input filter 30 into a frequency band which is less than half the signal sample rate of column decoder 26. The filtered audio signal is then applied to column decoder 26 through input amplifier 31 and automatic gain controller (AGC) 32. The analog signal sampled in the column decoder 26 is mapped to a drain voltage for the EEPROM cells of memory array 13 by using a pulse signal provided from a column high voltage generator 21 to an analog column read/write circuit 15 which then writes the analog signal into memory array 13. During a read operation, the analog data stored in memory array 13 is selected by an address output from address sequencer 24 and latched into column address buffer 25 and row address buffer 9 for output to column decoder 26 and row decoder 14, respectively, to produce a time varying analog output signal which is output through output filter 33 and output amplifier 34 to drive a speaker 35.
In the conventional circuit of FIG. 2, the column high voltage generator 21 generates a high voltage pulse signal ranging from 11V to 21V. The analog column read/write circuit 15 receives the high voltage pulse signal output from column high voltage generator 21 and uses the high voltage pulse signal to produce a high voltage data signal which corresponds to the input signal received from AGC 32. The analog column read/write circuit 15 then applies the high voltage data signal to the drain electrode of an EEPROM cell in memory array 13 so that the electric charge stored in the EEPROM cell corresponds to the input signal received from AGC 32. Column read/write circuit 15 reads the data in memory array 13 by comparing the voltage of the drain electrode of the selected EEPROM cell with the high voltage data signal produced from the pulse signal output from the column high voltage generator 21 to produce an analog output signal which is output through output filter 33 and output amplifier to drive speaker 35.
However, the solution of U.S. Pat. No. 4,890,259 is not particularly effective for storing digital data, although it is the first case where a high density IC analog signal writing and reading system has been commercially successful in improving the storage performance of an EEPROM by analog operation.